The present invention relates to the field of programmable integrated circuits and in particular, to techniques and circuitry for implementing a pattern detection and data alignment mechanism in a programmable logic device.
Integrated circuits are important building blocks of the modern age. Technology continues to evolve and integrated circuits continue to provide improved functionality. As integrated circuits improve, so do the electronics systems that are built using integrated circuits. There are many types of integrated circuit such as memories, microprocessors, application specific integrated circuits (ASICs), and programmable logic. Programmable logic integrated circuits such as PALs, PLDs, FPGAs, LCAs, and others are becoming more complex and continually evolving to provide more user-programmable features on a single integrated circuit. Modern programmable logic integrated circuits incorporate programmable logic including logic gates, products terms, or look-up tables. Programmable logic integrated circuits also included embedded user-programmable memory or RAM.
Despite the success of programmable logic, there is a continuing desire to provide greater functionality in a programmable logic integrated circuit, but at the same time, provide greater performance. Desired functionalities include high speed serial interfaces. These interfaces are needed especially as data and communications interfaces.
Data is transferred serially through a network. When serial data is input into an integrated circuit, the data is converted into parallel form for further processing and handling. However, when converting serial data into parallel form, it is important to form the parallel bits from the serial data using the correct byte or word boundaries. For example, the most significant bit (MSB) and least significant bit (LSB) of a byte of data should be in the correct positions of the byte of data. The byte of parallel data needs to be aligned properly from the serial stream. Once converted in a proper parallel data format with correct byte or word alignment, the integrated circuit, such as a programmable logic integrated circuit, may process the data.
In data transmission, there is typically a symbol or symbols (or pattern) that is used to denote the beginning of a frame boundary or some other unique symbol such as an idle character which can be used to achieve byte alignment. It is desirable to provide a technique to recognize or identify the symbol and align the serial data properly as rapidly and efficiently as possible, even though it may not be aligned within the parallel byte of data coming from a deserializer. As with circuitry for integrated circuits, the circuitry used to implement the approach should be area efficient.
Furthermore, the symbol or symbols for different serial or networking protocols are different or may change. It is costly to replace a “type A” integrated circuit with a “type B” integrated circuit to address different symbols. It is also costly to manufacture several types of integrated circuits where the only difference is the circuitry used to recognize a symbol and adhere to a particular protocol. Therefore, it is desirable to have one type integrated circuit which may be programmed or reprogrammed to recognize any symbol or a range of different symbols, so this integrated circuit may be used with different serial transfer or networking protocols. It is important that the circuitry used to implement the technique may be programmed, reprogrammed, altered, or changed easily, without a major change such as a mask change, in order to recognize different symbols and achieve byte or word alignment.
Therefore, there is a need to provide techniques and circuitry for implementing a serial-to-parallel conversion with pattern detect and byte alignment, especially as an input interface for programmable logic.